It’s called RAISE (Redundant Array of Independent Silicon Elements) and it is already done in ALL SSDs. the reason being is that the fastest commercially available NAND chips right now are only capable of 166 MT/s IIRC (Maybe 200?). Next year toggle 2 (400 MT/s) NAND should be available.

SSD controllers are like RAID controllers in that they come with number of available channels (sandforce = 8) so 8 NAND cells can be “striped” together. To saturate the BUS. As density and speed increase we see faster chips being raided together or additional controllers being tossed into the mix to create more channels. Blowing well past the SATA 6Gbps standard and necessitating PCIExpress slots.

Not necessarily RAID striping.

A few months back, we proposed a “SATA-IV” standard which ups the clock rate to 8G and adopts the 128b/130b “jumbo frame” now in the PCI-E 3.0 specification:

8G / 8 bits per byte = 1.0 GBps.

I don’t know if this is what they are planning, however; and, obviously, this requires upgrades to the controllers at both ends of the data cable.

Nevertheless, as we explained in a Thread posted in this Forum, this is a very logical extension of the PCI-E 3.0 “topology” — using flexible cables to supplement the hard-wired traces on motherboard layers:

https://www.thessdreview.com/Forums/ssd-discussion/1555.htm

MRFS