We need to reiterate 2 key features of PCIe Gen 3:
8 GHz clock rate AND 130b/128b “jumbo frames”.

By design, these 2 features result in 8G / 8b = ~1.0 GB/second throughput
at the chipset level, for a single x1 PCIe “lane”.

However, current 6G SSDs remain limited by
6 GHz clock rates AND 10b/8b “legacy frames”,
and the best are now bumping against this
“glass ceiling” e.g. 550 MB/second READS.

So, we can raise the ceiling by increasing the
clock rate to 8G (at least) or 12G and
keeping legacy frames, like this:

8G / 10b = 800 MB/second
12G / 10b = 1,200 MB/second

But, the PCIe Gen3 spec offers a wonderful opportunity
to “sync” it with all future SATA standards, i.e. by also adding
the 130b/128b “jumbo frame” to the SATA standard e.g.:

8G / 8b = ~1.0 GB/second per channel
12G / 8b = ~1.5 GB/second per channel
16G / 8b = ~2.0 GB/second per channel
… and so on.

Dropping 2 extra bits from every byte transmitted
should also eliminate a lot of overhead in
controllers at both ends of the data cables!

FYI: More details are at the Forums here:
“SATA-IV” Proposal: A Flexible Topology for PCIe 3.0

MRFS