Cadence Design Systems Develops New IP As NVMExpress Comes Into Its Own

Complete IP Subsystem Enables Fast Development of SoCs at Lower Cost

SAN JOSE, Calif., 15 May 2012

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today launched the industrys first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem is the industrys first to feature fully-integrated component IP, including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog. This high level of integration enables easy implementation of NVM Express in SoC designs.NVM Express is a specification that will speed the broader adoption of PCI Express-based SSDs by improving performance and reducing power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCI Express implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCI Express-based SSDs.Our studies find that PCI Express is poised to become the preferred embodiment of NAND in the enterprise, and this will lead to expanding adoption of the NVM Express protocol, said Jim Handy, director, Objective Analysis. Today several vendors produce PCI Express SSDs based on an SSD array architecture, but over time we expect these to yield to faster designs that remove the intervening step and allow NAND flash to communicate directly using an NVM Express interface, as supported by the Cadence suite.Cadence combined our expertise in interface IP, analog/mixed signal technologies, and system verification to offer customers a complete and full-featured NVM Express interface subsystem, said Martin Lund, senior vice president, Research and Development, SoC Realization Group, Cadence. Without this subsystem approach, SoC designers would need to source their interface component IP separately and drive integration on their own, often increasing their design risk and overall development time for new SoCs.

The controller used in the Cadence NVM Express solution supports advanced command management, data tiering and hardware command acceleration. The IP is highly configurable, allowing it to target the broad scope of applications possible with NVM Express. The included driver firmware offers an easy interface to the system firmware. The solution also includes a verification and test environment spanning from the PCI Express interface to the internal bus fabric.

Cadence offers a design methodology that uses the Cadence Virtual System Platform, NVM Express and PCI Express verifications models, Cadence Incisive® Software extensions and flash memory models to accelerate the design and integration of the Cadence NVM Express IP solution. These components provide a scalable verification and test platform for system-level software and hardware development and testing.

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